1. Field of the Invention
The present invention relates to a mobile communication terminal device and a variable gain circuit that is preferably installed, for example, in cellular phones compatible with the W-CDMA (Wideband-Code Division Multiple Access) method, PHS (Personal Handyphone System) phones or PDA (Personal Digital(Data) Assistants) having wireless communication capability.
2. Description of Related Art
The received power level distribution of antennas used in modern cellular phones spans a wide range from 80 dB to 100 dB. To cope with this, cellular phone receivers use an automatic gain control circuit (AGC circuit) that adjusts the signals received over this wide range to an optimum level so that the appropriate signals are transferred to the baseband A/D converter.
Analog control type circuits (VGA circuit: voltage-controlled gain amplifier) have been commonly used as AGC circuits to adjust the voltage serving as the control signal and use it to control the gain. Recently, however, digital control type circuits (PGA circuit: programmable gain amplifier) are being widely used that supply digital data as the control signal and control the gain discretely.
A typical PGA circuit is shown in FIG. 7. This PGA circuit is also capable of changing the gain of a PGA section 101, for example, in one decibel steps or from a minimum gain up to the maximum gain one step at a time, by supplying gain control information to each stage of a PGA section 101 from a gain control circuit 100 based on 3-wire signals (data signal, clock signal, and latch signal).
In this type of PGA circuit, when the PGA section 101 is controlled to a high gain, the self-offset DC voltage at each stage in the PGA section 101 is also amplified so that the output DC level reaches the reference voltage level (VDD level) or ground level (GND level) and the PGA circuit eventually saturates. Normal operation of the PGA circuit cannot be expected during this saturated state.
To solve this problem, a DC feedback circuit 102 is installed in this PGA circuit as shown in FIG. 7. This DC feedback circuit 102 detects direct current components (DC components) in the output signal, inverts the phase of the detected signal, and adds the detected signal to the input signal (negative feedback) by using an adder 103. This feedback process cancels out the change in the self-offset DC voltage and stabilizes the direct current value in this PGA circuit. Problems with PGA circuit saturating are in this way prevented.
When using this type of PGA circuit as a baseband amplifier for cellular phones, the cutoff frequency of a low-pass filter used as the DC feedback circuit 102 must be set to an extremely low value. If the cutoff frequency is not set to an extremely low value, then a lack of low frequency components in the input-to-output signal transfer characteristics will increase to a level that is not acceptable for baseband amplifiers.
However, the cutoff frequency level and the time constant of this DC feedback circuit 102 are in a trade-off relationship with each other. As the cutoff frequency is set lower, the time constant becomes larger. This creates the problem that time (DC voltage convergence time) is required for the DC voltage change to converge to the initial level.
More specifically, when the gain is switched, the DC voltage greatly varies at that gain switching timing as shown in FIG. 8. Also the time required for the DC voltage change to converge to the initial DC voltage will be longer when the cutoff frequency is set to a low value.
To shorten this DC voltage convergence time, a band switching signal is supplied to the DC feedback circuit 102 at the timing when the gain is switched as shown in FIG. 9. This band switching signal switches and controls the cutoff frequency that has been set at a low level, so that the cutoff frequency temporarily changes to a higher level. This also temporarily reduces the time constant of the DC feedback circuit 102 so that DC voltage convergence time can be shortened as shown in FIG. 10.
A variable gain amplifier system well known in the related art as a PGA circuit is disclosed in JP-A No. 36358/2001.
As stated above, the DC voltage convergence time can be shortened by switching the cutoff frequency of the DC feedback circuit 102. However, there is still the problem that merely changing the cutoff frequency will not control the large change in DC voltage that occurs immediately after the gain is switched. This large change in DC voltage might hinder stable operation in latter stages downstream of the PGA circuit.